pkg-descr

Icarus Verilog is a Verilog simulation and synthesis tool. It
operates as a compiler, compiling source code writen in Verilog
(IEEE-1364) into some target format. For batch simulation, the
compiler can generate C++ code that is compiled and linked with
a run time library (called "vvm") then executed as a command to
run the simulation. For synthesis, the compiler generates netlists
in the desired format.

The compiler proper is intended to parse and elaborate design
descriptions written to the IEEE standard IEEE Std 1364-2000. The
standard proper is due to be release towards the middle of the
year 2000. This is a fairly large and complex standard, so it will
take some time for it to get there, but that's the goal.

WWW: http://www.icarus.com/eda/verilog/

pkg-plist

bin/iverilog
bin/iverilog-vpi
bin/vvp
include/_pli_types.h
include/acc_user.h
include/ivl_target.h
include/veriuser.h
include/vpi_user.h
lib/ivl/cadpli.vpl
lib/ivl/edif-s.conf
lib/ivl/edif.conf
lib/ivl/edif.tgt
lib/ivl/fpga-s.conf
lib/ivl/fpga.conf
lib/ivl/fpga.tgt
lib/ivl/ivl
lib/ivl/ivlpp
lib/ivl/null-s.conf
lib/ivl/null.conf
lib/ivl/null.tgt
lib/ivl/system.sft
lib/ivl/system.vpi
lib/ivl/vvp-s.conf
lib/ivl/vvp.conf
lib/ivl/vvp.tgt
lib/ivl/xnf-s.conf
lib/ivl/xnf.conf
lib/libveriuser.a
lib/libvpi.a
@dirrm lib/ivl